Correlator

Introduct

The basic layout of the lag correlator is shown in Figure 1. It is comprised of two tapped delay lines with a set of analogue multipliers fed from the taps. Each multiplier measures the degree of correlation at a particular time delay, or lag, between the two input signals. Taken together, the outputs of the multipliers provide a measurement of the cross correlation function of the two inputs. A Fourier transform of the cross correlation function yields the cross power frequency spectrum, which provides the required measure of phase and amplitude at a discrete set of frequencies across the band.

Specifications

Bandwidth - > 16GHz
Frequency resolution - < 3GHz
19 antennas ¡V 171 baselines
4 polarisation products per baseline
Time resolution ¡V 0.1 seconds

Major Challenges

Wide bandwidth
Required frequency resolution
Complex interconnect from antennas to correlator

Proposed Solutions

Analogue multipliers 2 to 20 GHz
Sampled lag domain analogue correlator giving 8 frequency channels per product
Modular array layout

Wideband Analogue Multiplier( Possible implementations)

Active analogue multiplier cells
e.g. Gilbert Cell Multiplier
- CSIRO ATNF
Wideband double balanced mixer
- Carnegie Mellon University
fig.1:Lag Correlator

Backend Processing Circuit

The Backend Processing Circuit transfers the analog signal from the Lag-Correlating Multipliers into digital data sequence and accumulates them with programmable counters, which acts as a long-time integration process.There exists a Master-Slave structure in the processing circuit: A PLL (Phase-Lock-Loop) is used in the Master Circuit to adjust the control voltage of the VCO (voltage-controlled oscillator ) in order to generate a clock which has the same frequency as the reference clock (4MHz). The 17 Slave VCO¡¦s are biased at the adjusted control voltage from PLL and oscillate at the same reference frequency. The input signal is incorporated to the bias voltage and the output oscillating frequency will change according to the input signal. Analog part works as VFC (voltage-to-frequency converter). The 17 slave clocks are used to trigger the respective 24-bit up/down counter to accumulate the digital data. The up/down function is controlled by phase-switching. At the end of an integration interval, the 17 24-bit data, i.e. 408 bits are scanned out serially. The whole circuit is packaged into chip and has been tested and verified.

fig.2: From Multiplier followed by an amplifier LPF

Mixer Array Lag Correlator

Antennas read signals off the sky with path difference depending on source angle Signals travel along paths of equal length to Correlator Inside correlator delay lines remove signal path delays Each element of mixer array in the correlator measures the power from a particular direction The correlator also allows measurement of the spectrum of any signal detected.

fig.3: Lag Correlator Ceramic Substrate Layout