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Research Gallery > The Yuan Tseh Lee Array (YTLA)

Research Gallery

The Yuan Tseh Lee Array (YTLA)

Clock Distribution Drawer for YTLA
Image Credit: Jen-Chieh Cheng, Johnson Han, Derek Kubo
Clock Distribution Drawer for YTLA
Clock Distribution Drawer
This 2U integrated module was designed by Derek Kubo, and assembled and tested by Jen-Chieh Cheng and Johnson Han for YTLA project. The main function of this module is to generate and distribute 16 channels of a 1.6GHz clock signal with +12 dBm (+/-0.2dB) output power for each channel. An extra 10MHz input signal is essential for phase lock reference of internal Valon 5008 Dual Synthesizer. Both Valon output channels can be adjust in frequency (138MHz ~ 4400MHz) and in power (-2 ~ 7dBm) through a control software (Windows OS). The output clock signals are provided to Analog-to-Digital Converters (ADCs) located within the ROACH-2 chassis.
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