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Research Gallery > The Yuan Tseh Lee Array (YTLA, formerly AMiBA)

Research Gallery

The Yuan Tseh Lee Array (YTLA, formerly AMiBA)

Clock Distribution Chassis, YTLA Project
Image Credit: Jen-Chieh Cheng, Johnson Han, Derek Kubo
Clock Distribution Chassis, YTLA Project
This is a photo of the YTLA clock distribution drawer packaged in a standard rack mount 2U height EMI chassis.
This unit was designed by Derek Kubo and assembled and tested by Jen-Chieh Cheng and Johnson Han for the YTLA project. The main function of this unit is to generate a 2.240 GHz clock signal and is based on a Valon 5009 programmable synthesizer that is phase locked to our external 10 MHz GPS reference. 16 copies of this clock are produced each with an output level of +12 dBm (+/-0.2 dB). A second auxiliary clock output is available and can be programmed independently from the first using Windows based control software. The output clock signals from this unit are provided to 14 separate ROACH-2 chassis each of which contains a pair of 5 Gsps high speed ADC boards that were developed in-house by Homin Jiang.
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