Senior Research Engineer
My research interests are mainly in system integration that involves software and hardware. I have developed a 5 giga sample rate ADC board for CASPER(Collaboration for Astronomy Signal Processing and Electronics Research) community, including the EHT telescope. The 5G ADC board is a part of the EHT backend system which has captured the first black hole image. In 2016-2020, I developed an even faster ADC, 16Giga sample rate that might be a candidate for the next generation EHT ADC board. I am acquiring a game-changing ADC/FPGA platform, it will have a very high ADC sampling rate. I am targeting that board for next generation GLT, LMT and other high frequency telescopes. Besides ADC development, I have been interested in the high-speed digital electronics, digital signal processing, and FPGA programming. We have built a correlator system for YTLA which is located in Mauna Loa , Hawaii. From 2020, I have been working on a beamformer/2D FFT system for BURSTT using RFSoC FPGA boards. BURSTT has 128 antennas implemented on the main site